The present invention relates generally to the field of semiconductor manufacturing and, more particularly, to the use of a test structure for measuring electrical and dimensional characteristics.
A conventional integrated circuit device, such as a microprocessor, is typically comprised of many thousands of semiconductor devices, e.g., transistors, formed above the surface of a semiconductive substrate. For the integrated circuit device to function, the transistors must be electrically connected to one another through conductive interconnect structures. Many modern integrated circuit devices are very densely packed, i.e., there is very little space between the transistors formed above the substrate. Thus, these conductive interconnect structures must be made in multiple layers to conserve plot space on the semiconductive substrate.
The conductive interconnect structures are typically accomplished through the formation of a plurality of conductive lines and conductive plugs formed in alternative layers of dielectric materials formed on the device. As is readily apparent to those skilled in the art, the conductive plugs are means by which various layers of conductive lines, and/or semiconductor devices, may be electrically coupled to one another. The conductive lines that connect the various interconnect structures are commonly formed in trenches defined in the dielectric layers.
The term “contact” is generally used to define an interconnect structure (e.g., using polysilicon or metal) to underlying polysilicon or silicon (e.g., a gate electrode or a source/drain region of a transistor), while a “via” denotes a metal to metal interconnect structure. In either case, a contact opening is formed in an insulating layer overlaying the conductive member. A second conductive layer is then formed in the contact opening and electrical communication is established with the conductive member.
During the fabrication of semiconductor devices on a wafer, test structures are commonly formed on the wafer coincident with the discrete semiconductor die. The test structures typically include trenches filled with copper similar in construct to the actual trenches and lines that comprise the functional semiconductor devices. Because the processes used to form functional devices is also used to form the test structures, characteristics of the semiconductor devices may be inferred by evaluating the results of testing on the test structures. Defects that exist in the test structure are likely to be similar in type and distribution to those present in the semiconductor devices.
For example, capacitance and resistance tests performed on the test structures give insight as to the capacitance and resistance properties of the semiconductor devices. Test structures may be formed on the same wafer with actual devices, or alternatively, they may be formed on dedicated test wafers on which no saleable devices are present. Typically, different test structures are used to measure different parameters associated with the devices. For example, an interleaved comb structure may be used to measure capacitance, thus providing a metric related to the dielectric constant of the insulating layer in which the lines are formed. A separate structure may be used to measure resistance. Yet another structure may be used to measure physical characteristics, such as critical dimensions.
The various test structures are disposed in multiple locations across a wafer. Due to the large number of discrete steps involved in the manufacture of semiconductor devices, there are many sources of variation that contribute to the physical and electrical characteristics of the completed device. Some sources of variation affect an entire wafer, while others have localized effects, i.e., cross wafer or cross-die variation. Due to the spatial distribution of the test structures, it is potentially difficult to discern between sources of variation to enable the processes to be adjusted to achieve improved results.
This section of this document is intended to introduce various aspects of art that may be related to various aspects of the present invention described and/or claimed below. This section provides background information to facilitate a better understanding of the various aspects of the present invention. It should be understood that the statements in this section of this document are to be read in this light, and not as admissions of prior art. The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.